### Abstract

In this paper, we consider a type of on-line, traffic scheduling problem in input queued, crossbar switches. The input to a problem, at each time step, is a set of desired traffic rates. These traffic rates in general cannot be exactly achieved since they assume arbitrarily small fractions of packets can be transmitted at each time step. The goal of the traffic scheduling problem is to closely approximate the given sequence of traffic rates by a sequence of switch uses in which only whole packets are sent. The focus of this paper is bounding the costs incurred in using such an approximation, in terms of the additional buffer size required. We establish universal bounds on the additional buffer size due to sending only whole packets; these bounds do not depend on the particular distribution of the input traffic, require no speedup, and guarantee 100% throughput. Specifically, for an N × N input queued, crossbar switch, an on-line, packetizing algorithm is presented that guarantees 100% throughput with a buffer requirement of (N + 1) ^{2} /4 packets per input port with no speedup. The algorithm can be improved to run in O(N log N) time, using a fast algorithm for edge-coloring bipartite multi-graphs. In the reverse direction, it is shown for an N × N input queued, crossbar switch, that any on-line, packetizing algorithm with no speedup requires a buffer size of N/e - 2 packets per input port. We also extend the main packetizing algorithm in this paper to a general class of switch architectures.

Original language | English (US) |
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Title of host publication | Proceedings - IEEE INFOCOM |

Pages | 1126-1134 |

Number of pages | 9 |

Volume | 2 |

DOIs | |

State | Published - 2004 |

Externally published | Yes |

Event | IEEE INFOCOM 2004 - Conference on Computer Communications - Twenty-Third Annual Joint Conference of the IEEE Computer and Communications Societies - Hongkong, China Duration: Mar 7 2004 → Mar 11 2004 |

### Other

Other | IEEE INFOCOM 2004 - Conference on Computer Communications - Twenty-Third Annual Joint Conference of the IEEE Computer and Communications Societies |
---|---|

Country | China |

City | Hongkong |

Period | 3/7/04 → 3/11/04 |

### Fingerprint

### Keywords

- Combinatorics
- Deterministic network calculus
- Graph theory

### ASJC Scopus subject areas

- Electrical and Electronic Engineering
- Hardware and Architecture

### Cite this

*Proceedings - IEEE INFOCOM*(Vol. 2, pp. 1126-1134) https://doi.org/10.1109/INFCOM.2004.1356999

**Universal bounds on buffer size for packetizing fluid policies in input queued, crossbar switches.** / Rosenblum, Michael Aaron; Goemans, Michel X.; Tarokh, Vahid.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - IEEE INFOCOM.*vol. 2, pp. 1126-1134, IEEE INFOCOM 2004 - Conference on Computer Communications - Twenty-Third Annual Joint Conference of the IEEE Computer and Communications Societies, Hongkong, China, 3/7/04. https://doi.org/10.1109/INFCOM.2004.1356999

}

TY - GEN

T1 - Universal bounds on buffer size for packetizing fluid policies in input queued, crossbar switches

AU - Rosenblum, Michael Aaron

AU - Goemans, Michel X.

AU - Tarokh, Vahid

PY - 2004

Y1 - 2004

N2 - In this paper, we consider a type of on-line, traffic scheduling problem in input queued, crossbar switches. The input to a problem, at each time step, is a set of desired traffic rates. These traffic rates in general cannot be exactly achieved since they assume arbitrarily small fractions of packets can be transmitted at each time step. The goal of the traffic scheduling problem is to closely approximate the given sequence of traffic rates by a sequence of switch uses in which only whole packets are sent. The focus of this paper is bounding the costs incurred in using such an approximation, in terms of the additional buffer size required. We establish universal bounds on the additional buffer size due to sending only whole packets; these bounds do not depend on the particular distribution of the input traffic, require no speedup, and guarantee 100% throughput. Specifically, for an N × N input queued, crossbar switch, an on-line, packetizing algorithm is presented that guarantees 100% throughput with a buffer requirement of (N + 1) 2 /4 packets per input port with no speedup. The algorithm can be improved to run in O(N log N) time, using a fast algorithm for edge-coloring bipartite multi-graphs. In the reverse direction, it is shown for an N × N input queued, crossbar switch, that any on-line, packetizing algorithm with no speedup requires a buffer size of N/e - 2 packets per input port. We also extend the main packetizing algorithm in this paper to a general class of switch architectures.

AB - In this paper, we consider a type of on-line, traffic scheduling problem in input queued, crossbar switches. The input to a problem, at each time step, is a set of desired traffic rates. These traffic rates in general cannot be exactly achieved since they assume arbitrarily small fractions of packets can be transmitted at each time step. The goal of the traffic scheduling problem is to closely approximate the given sequence of traffic rates by a sequence of switch uses in which only whole packets are sent. The focus of this paper is bounding the costs incurred in using such an approximation, in terms of the additional buffer size required. We establish universal bounds on the additional buffer size due to sending only whole packets; these bounds do not depend on the particular distribution of the input traffic, require no speedup, and guarantee 100% throughput. Specifically, for an N × N input queued, crossbar switch, an on-line, packetizing algorithm is presented that guarantees 100% throughput with a buffer requirement of (N + 1) 2 /4 packets per input port with no speedup. The algorithm can be improved to run in O(N log N) time, using a fast algorithm for edge-coloring bipartite multi-graphs. In the reverse direction, it is shown for an N × N input queued, crossbar switch, that any on-line, packetizing algorithm with no speedup requires a buffer size of N/e - 2 packets per input port. We also extend the main packetizing algorithm in this paper to a general class of switch architectures.

KW - Combinatorics

KW - Deterministic network calculus

KW - Graph theory

UR - http://www.scopus.com/inward/record.url?scp=8344243758&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=8344243758&partnerID=8YFLogxK

U2 - 10.1109/INFCOM.2004.1356999

DO - 10.1109/INFCOM.2004.1356999

M3 - Conference contribution

AN - SCOPUS:8344243758

SN - 0780383559

VL - 2

SP - 1126

EP - 1134

BT - Proceedings - IEEE INFOCOM

ER -