Ultra-low power neural stimulator for electrode interfaces

Power loss at the output stage of conventional constant current neural stimulators is notably high. This is particularly disadvantageous for applications in implantable systems where power budget is limited. We present a novel electrical stimulator architecture for significantly reduced power loss and low noise operation. The system generates a calibrated output voltage profile for driving electrode impedance with an approximate biphasic current stimulation. The stimulator utilizes switched-capacitor output driver stage and low speed operations for substantial reduction in power loss. The hardware is capable of generating on-demand clock signals for appropriate switching events through a feedback mechanism. The self-clocking ultra-low power stimulator front-end and its controller exhibits quasi-stable quiescent power consumption of 3.75 μW and raw efficiency up to 98%. The low power stimulator architecture consumes nearly 70% less power than conventional linear mode stimulators and half of the reported state-of-The art design. Output peak-to-peak noise down to 20 mV is achieved through this design. Demonstrations are shown with RC impedance, platinum-iridium electrode in saline solution and in-vivo somatosensory cortex stimulation.