LNS architectures for model predictive control processors

Jesus Garcia, Leonidas Bleris, Mark G. Arnold, Mayuresh V. Kothare

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a research on arithmetic units targeted to implement model predictive control (MPC) in a custom embedded processor. A novel hardware implementation of cotransformation for the calculation of addition and subtraction in the Logarithmic Number System (LNS) is proposed. This architecture provides a small ROM-less adder/subtracter, with longer operation latency than other LNS techniques, but easily pipelineable. These characteristics make it very adequate for implementing the datapath of custom MPC embeddable microprocessors. A review of the arithmetic customization process is presented, including: an analysis of the finite precision problem, modifications to the standard MPC algorithm that simplify embedding the application, and the reasons that suggest better performance of LNS over standard floating-point (FP) architectures. The proposed arithmetic unit architecture for 16-bit LNS is fully synthesized for ASIC, and compared with an equivalent FP implementation. Area and clock cycle estimates are compared. Finally, considerations on low-precision implementations of LNS arithmetic units are provided, and an embedded-ROM implementation of addition/subtraction in LNS is proposed and analyzed.

Original languageEnglish (US)
Title of host publicationCASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Pages79-84
Number of pages6
StatePublished - 2004
Externally publishedYes
EventCASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - Washington, DC, United States
Duration: Sep 22 2004Sep 25 2004

Other

OtherCASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
CountryUnited States
CityWashington, DC
Period9/22/049/25/04

Keywords

  • Cotransformation
  • FWL
  • LNS
  • MPC
  • Reduced precision

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Garcia, J., Bleris, L., Arnold, M. G., & Kothare, M. V. (2004). LNS architectures for model predictive control processors. In CASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 79-84)