The results of a systematic study undertaken to identify process related defects introduced during the fabrication of low-k dielectric based copper interconnects was presented. The copper electroplating process was examined to reduce the number of plating related defects. The defects from the electroplating process were classified into a defect pareto chart. Efforts were made to reduce defects that were known to be detrimental in device performance.
ASJC Scopus subject areas
- Chemical Engineering(all)