Design of a zero delay subband acoustic echo canceller

Jiande Chen, Joos Vandewalle, Hugo Bes, Ingrid Evers, Paul Janssens

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The design of a zero delay subband acoustic echo canceller (AEC) is presented. The filter banks are realized by a simplified weighted overlap-add method and oversampling is used to avoid aliasing problems. Complex adaptive filters are used within the filter banks. The design considerations and hardware implementation are discussed in some detail. Parallel processing, pipeline techniques, short machine cycle time and dedicated buses are applied in the hardware implementation to realize a 2048-tap AEC in a single custom chip with existing technology. Simulation results are given and its advantages are shown to be sufficient echo return loss, echo removal in the whole frequency range, and computational saving.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1325-1328
Number of pages4
ISBN (Print)9517212402
StatePublished - Dec 1 1988
Externally publishedYes

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2
ISSN (Print)0271-4310

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Chen, J., Vandewalle, J., Bes, H., Evers, I., & Janssens, P. (1988). Design of a zero delay subband acoustic echo canceller. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1325-1328). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2). Publ by IEEE.