The design of a zero delay subband acoustic echo canceller (AEC) is presented. The filter banks are realized by a simplified weighted overlap-add method and oversampling is used to avoid aliasing problems. Complex adaptive filters are used within the filter banks. The design considerations and hardware implementation are discussed in some detail. Parallel processing, pipeline techniques, short machine cycle time and dedicated buses are applied in the hardware implementation to realize a 2048-tap AEC in a single custom chip with existing technology. Simulation results are given and its advantages are shown to be sufficient echo return loss, echo removal in the whole frequency range, and computational saving.