CHIP-PLACEMENT ALIGNMENT TECHNIQUE.

M. S. Chester, M. A. Lavin, Russell H Taylor

Research output: Contribution to journalArticle

Abstract

Chip positioning by relating the positions of solder balls and mating connection pads (vias) indirectly - by determining the positional relationship of balls and of vias separately to a reference mark, rather than to each other - increases total positional accuracy and convenience. Two measured relationships are outlined. They can be used to determine the solder ball/via pad misalignment and from that determination produce a command to the placement tool to correct the misalignment.

Original languageEnglish (US)
Pages (from-to)3653-3655
Number of pages3
JournalIBM technical disclosure bulletin
Volume27
Issue number6
Publication statusPublished - Nov 1984
Externally publishedYes

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chester, M. S., Lavin, M. A., & Taylor, R. H. (1984). CHIP-PLACEMENT ALIGNMENT TECHNIQUE. IBM technical disclosure bulletin, 27(6), 3653-3655.