A custom-made algorithm-specific processor for model predictive control

Panagiotis D. Vouzis, Leonidas G. Bleris, Mark G. Arnold, Mayuresh V. Kothare

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an algorithm-specific processor for embedded Model Predictive Control (MPC). After analyzing the computational cost of MPC, via profiling, we observe that the optimizations associated with MPC are dominated by operations on real matrices. To overcome this bottleneck we propose connecting a limited resource host processor with an algorithm-specific matrix processor, whose architecture is described. The matrix processor uses a 16-bit Logarithmic Number System (LNS) arithmetic unit to carry out the required arithmetic operations. The proposed architecture is implemented using a Hardware Description Language (HDL) and subsequently it is synthesized and emulated on a Field Programmable Gate Array (FPGA). The timing and area cost results are presented and analyzed.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Industrial Electronics
Pages228-233
Number of pages6
Volume1
DOIs
StatePublished - 2006
Externally publishedYes
EventInternational Symposium on Industrial Electronics 2006, ISIE 2006 - Montreal, QC, Canada
Duration: Jul 9 2006Jul 13 2006

Other

OtherInternational Symposium on Industrial Electronics 2006, ISIE 2006
CountryCanada
CityMontreal, QC
Period7/9/067/13/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Control and Systems Engineering

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    Vouzis, P. D., Bleris, L. G., Arnold, M. G., & Kothare, M. V. (2006). A custom-made algorithm-specific processor for model predictive control. In IEEE International Symposium on Industrial Electronics (Vol. 1, pp. 228-233). [4077928] https://doi.org/10.1109/ISIE.2006.295597