A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition

Chao Yuan, Kian Ann Ng, Yong Ping Xu, Shih Cheng Yen, Nitish V Thakor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper reports a high-performance low-power and area-efficient single-ended SAR ADC for neural signal acquisition. The proposed 10-bit ADC features a novel symmetrical DAC switching technique that resolves the signal-dependent comparator offset voltage problem in conventional single-ended SAR ADCs, and improves the ADC's ENOB. Combined with an existing LSB single-sided switching method, the proposed switching scheme reduces DAC switching energy by 92% and capacitor array area by 50%. Besides, the proposed ADC also eliminates the need for any power consuming Vcm generation circuit, making it more suitable for low-power System-on-Chip (SoC) integration. The 10-bit prototype ADC is fabricated in a standard 0.18-μm CMOS technology. Operating at 1.0 V power supply and 100 kS/s, the proposed ADC achieves 58.83 dB SNDR and 63.6 dB SFDR for a 49.06 kHz input signal. The maximum ENOB is 9.8-bit for low frequency input signal; and the minimum ENOB is 9.48-bit at the Nyquist input frequency. The average power consumption is 1.72 μW and the fig re-of-merit (FoM) is 24.1 fJ/conversion-step.

Original languageEnglish (US)
Title of host publication2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467371919
DOIs
StatePublished - Jan 19 2016
Externally publishedYes
Event11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China
Duration: Nov 9 2015Nov 11 2015

Other

Other11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
CountryChina
CityXiamen, Fujian
Period11/9/1511/11/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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